1. Field of Invention
The present invention relates to a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof; particularly, it relates to such DDDMOS device and manufacturing method thereof wherein the DDDMOS device is formed by common process steps which also form a low voltage device.
2. Description of Related Art
FIGS. 1A-1B show a cross-section view and a top view of a prior art double diffused drain metal oxide semiconductor (DDDMOS) device 100, respectively. As shown in FIGS. 1A-1B, a P-type substrate 11 has multiple field oxide regions 12 by which a device region of the DDDMOS device 100 is defined. The field oxide region 12 for example is a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure, the former being shown in the figures. The DDDMOS device 100 includes a gate 13, a drift region 14, a source 15, a drain 16, and a well 17. The drift region 14, the source 15 and the drain 16 are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. The source 15 and the drain 16 are beneath the gate 13 and at different sides thereof respectively. The well 17 and the well contact 17a are defined by lithography process steps and formed by ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. FIG. 1B is a top view of the DDDMOS device 100 showing the location arrangement of the aforementioned regions.
The DDDMOS device 100 is a high voltage device designed for applications requiring higher operation voltages. In general, a high voltage device refers to a device having a voltage swing larger than 5V between its high and low operation voltages, and a low voltage device refers to a device having a voltage swing smaller than 5V between its high and low operation voltages. If the DDDMOS device is to be integrated with the low voltage device in one substrate, due to constraints in the manufacturing process, i.e., because both devices share the same process parameters, the breakdown voltage and the conduction resistance are usually not optimized. In order not to sacrifice the breakdown voltage and the conduction resistance, additional manufacturing process steps are required, that is, at least one additional lithography process and one additional ion implantation process are required in order to provide different ion implantation parameters to achieve the required breakdown voltage and the conduction resistance, but this increases the cost.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a DDDMOS device and a manufacturing method thereof, wherein the process steps for forming the low voltage device are also applied to forming the DDDMOS device so that the manufacturing cost is not substantially increased, while the DDDMOS device may have an enhanced performance.